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Q-BUS & UNIBUS PDP-11 FAMILY OF COMPUTERS

Table 1: Processor Information

  LSI-11 11/10
11/05 		11/15 11/20 11/40
11/35 		----- 11/45 -----
Memory Core, MOS, ROM Core Core Core Bipolar MOS Core
Reg to Reg Transfer 3.5 µs 3.7 µs 2.3 µs 0.9 µs 0.3 µs 0.45 µs 0.9 µs
Max Memory (Words) 32K 28K 28K 124K 124K 124K
Max Address Space 32K 32K 32K 128K 128K 128K
General Purpose Regs 8 8 8 8 16
Stack Processing Yes Yes Yes Yes Yes
Micro-programmed Yes Yes No Yes Yes
Instructions Basic Set + XOR,
SOB, MARK, SXT,
RTT, MTPS, MFPS		 Basic Set Basic Set Basic Set +
XOR, SOB, MARK,
SXT, RTT		 Same as 11/40 +
MUL, DIV, ASH,
ASHC, SPL
Extended Arithmetic
(hardware) 		Option (internal)
MUL, DIV,
ASH, ASHC		 Option (external) option (external) Option (internal)
MUL, DIV,
ASH, ASHC		 Standard (internal)
Floating Point Option, FADD,
FSUB, FMUL, FDIV		 Software only Software only Hardware option
32-bit word		 Hardware option
32 or 64-bit word
Stack Limit Address None 400 (fixed) 400 (fixed) 400 or
programmable
(option)		 programmable
Memory Management not available not available not available option
MFPI, MTPI		 option MFPI, MFPD
MTPI, MTPD
Modes 1 1 1 1 std, 2 opt 3
Automatic Priority
Interrupt 		1-line
multi-level		 4-line
multi-level		 1-line
multi-level		 4-line
multi-level		 4-line
multi-level		 4-line
multi-level +
8 software levels
Power Fail and
Auto-restart 		standard standard option standard standard standard
Source: DIGITAL LSI-11 PDP11/03 Processor Handbook, 1975 (Appendix C)

Table 2: Relative performance for UNIBUS and Q-BUS PDP-11 systems
(VAX-11/780 = 1.00 unit of performance)

PDP-11 UNIBUS PDP-11 Q-BUS MicroPDP-11 Q-BUS
11/04 0.11 11/03 0.01 11/23 0.10
11/24 0.18 11/23 0.05 11/53 0.29
11/34 0.20 11/23+ 0.10 11/73 0.45
11/44 0.42     11/83 0.72
11/70 0.60     11/93 0.90
11/84 0.72        
11/94 0.90        
Source: DIGITAL CPU Upgrade Guide, Spring-Summer 1992

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Started: 13-Feb-2006    Revised: 07-Mar-2006